The present invention relates to a semiconductor device and a technology of manufacturing the same, and can suitably be utilized, for example, for semiconductor devices having a power MOSFET (Power Metal Oxide Semiconductor Field Effect Transistor) of a super junction structure.
The super junction structure can satisfy both a low conduction resistance and a high junction breakdown voltage by arranging periodically narrow-pitched p-n junction cells. However, the outer peripheral part of the p-n junction cell is inevitably not of a periodic structure (not of a super junction structure) and, therefore, some ways and means for obtaining a high breakdown voltage without using a super junction structure are required in the outer peripheral part of the p-n junction cell.
For example, in US Patent No. 2009085147 (Patent Document 1) and US Patent No. 2005181564 (Patent Document 2), there are disclosed technologies of obtaining easily a high breakdown voltage by forming the outer peripheral part with the same conductivity type as that of a conduction layer and making the impurity concentration in the outer peripheral part lower than that in a unit cell.
In US Patent No. 2006231915 (Patent Document 3), there is disclosed a technology of covering the outer peripheral part with a broad and thick insulating film, in order to obtain a high outer periphery breakdown voltage.
In US Patent No. 2005181577 (Patent Document 4), there is disclosed a technology of not introducing an impurity into the side face of a trench in the outer peripheral part, in order to obtain a high outer periphery breakdown voltage.